This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-272072, filed Sep. 7, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM), particularly relates to, in the semiconductor memory device having a plurality of banks in which memory elements of a MOS type of transistor structure are formed with the memory elements arranged in a matrix form, the semiconductor memory device having an arrangement in which a certain bank can be read while erase or write is being performed in another bank, and it is utilized for a flash erasable semiconductor memory device (flash memory).
2. Description of the Related Art
A NMOS transistor having double layer stacked gate structure on a double well formed on a semiconductor substrate is known as a memory cell of the EEPROM.
FIG. 4 is a cross-sectional view showing an example of a cell including the NMOS transistor having the double layer stacked gate structure.
In FIG. 4, reference numeral 30 is a P type substrate (Psub), 31 is an N type well (Nwell) and 32 is a P type well (Pwell) formed in the N type well. In the N type well 31, a well leading electrode is formed of an N+type diffusion layer 33. In the P type well 32, a source S and a drain D of the NMOS transistor are formed by an N+type diffusion layer 34 and the well leading electrode of the well is formed by a P+ type diffusion layer 35.
A floating gate FG made of a poly-crystalline silicon layer of a first layer is formed on a gate insulation film 36, a control gate CG made of the poly-crystalline silicon layer of a second layer is formed with the control gate CG separated by a insulation film 37.
In the actual semiconductor memory device, a plurality of cells are arranged in a matrix form on one well, any one of cells is selected by a plurality of row lines WL connected to the control gate CG of the cell of each row and a plurality of column lines BL connected to the drain D of the cell of each row. The source S, the N type well 31 and the P type well 32 of all cells are commonly connected with a source line SL.
Operation of the cell will be briefly described as an example of an NOR type memory cell which applies high voltage to the channel to erase.
In-case of erasing data, for example, by applying 10V to the source line SL, the voltage of 10V is applied to the source S, the N type well 31 and the P type well 32 of the cell. By applying, for example, xe2x88x927V to all row lines WL, the voltage of xe2x88x927V is applied to all control gates CG. The drain D is made to be a floating state. At this point, electrons in the floating gate FG are emitted into a channel by Fowler-Nordheim (FN) tunneling. A threshold of the cell becomes lower at this state, and data of this erase state is normally referred to as xe2x80x9c1xe2x80x9d.
In case of writing data, for example, any one of a plurality of row lines WL is set to 9V, for example, any one of a plurality of column lines BL is set to 5V, for example, and the source line SL is set to 0V in order to select the cell to be written. At this point, in the selected cell, electrons are injected into the floating gate FG by hot electron injection. The threshold of the cell becomes higher at this state, and data of this write state is normally referred to as xe2x80x9c0xe2x80x9d.
In case of reading data, for example, any one of a plurality of row lines WL is set to, for example, 5V, any one of a plurality of column lines BL is set lower voltage (for example, 0.7V) and the source line SL is set to 0V in order to select the cell to be read. At this point, in case that the selected cell is in the write state (data are xe2x80x9c0xe2x80x9d), current does not flow because the cell is not turned on. On the other hand, in case that data of the selected cell is in the erase state (data are xe2x80x9c1xe2x80x9d), cell current of about 40 xcexcA flows because the cell is turned on. The amplitude of the current is sensed and amplified by a sense amplifier circuit (not shown) or the like to read data.
Though the NOR type memory cell which applies high voltage to the channel to erase is taken as the example in the above description of the operation, the same operation is also performed in a memory cell which applies high voltage to the source to erase.
Recently, the semiconductor memory device is used, for example, as a component of a portable device and utilized for storing various programs and personal data, there are strong demands storing programs or data in one semiconductor memory device in order to reduce the number of required memory chips in a system.
However, required time for re-writing data becomes relatively longer in case that the cell shown in FIG. 4 is used. Normally it takes about 10 xcexcsec to write data and it takes about several hundreds of msec to as much as several sec for a block to erase data, it is impossible to read data during re-writing the data.
A memory system known as a RWW (Read While Write) type, which is able to read data in a certain memory area while data are written or erased in another memory area, has been proposed.
The present applicant has proposed Japanese Patent Application No. 2000-127106 of xe2x80x9csemiconductor devicexe2x80x9d which can concretely realize a flash memory capable of writing or erasing data and reading data simultaneously by using the NMOS transistor of the double layer stacked gate structure shown in FIG. 4 as the cell.
FIG. 5 shows an example of concrete arrangement of a part of a flash memory, which is proposed at the moment, capable of writing or erasing data and reading out data simultaneously.
As shown in FIG. 5, in a plurality of banks BNK0 to BNKk, one or a plurality of block circuit groups (in the example, BA0 to BAi) are arranged in a first direction, the plurality of banks BNK0 to BNKk are arranged in a second direction perpendicular to the first direction.
In each of the block circuit groups BA0 to BAi, electrically rewritable memory cells having the MOS structure are arranged in a matrix form respectively, a cell array MA0 divided by an erase unit, a sub row selection decoder RS0, the row line WL, the column line BL, a column selection gate CG0 and a block decoder BD0 are provided.
In the banks BNK0 to BNKk, main row selection decoders RM0 to RMk, j data line switching circuits DLSW0 to DLSWk and power supply decoders VD0 to VDk are provided correspondent to each bank.
In each of the banks BNK0 to BNKk, main row selection line Mi connected commonly to the block circuit groups BA0 to BAi in the same bank and j sub data lines SDLj (for example, eight lines or sixteen lines) are also formed.
The sub data lines SDLj on the block circuit groups BA0 to BAi in the same bank are formed by a first wiring layer in the first direction, connected to j column selection gates CG0 in each of block circuit groups BA0 to BAi and connected correspondent to the j data line switching circuits DLSW0 to DLSWk every bank BNK0 to BNKk.
The power supply decoders VD0 to VDk are circuit groups performing power supply control in case of write or erase by a bank unit and decode control for selecting the memory cell.
Out of the bank areas, j main data lines MDL_Rj for read, in which data of the memory cell in a bank selected by read operation (a first operation mode) are read through the j sub data lines and the j data line switching circuits DLSW0 to DLSWk, are formed by a second wiring layer in the second direction. The j main data lines MDL_Rj for read are connected to j amplifier circuits SA_Rj for read.
Out of the bank areas, j main data lines MDL_Aj for auto, in which data of the memory cell in a bank selected by write or erase operation (a second operation mode) are read through the j sub data lines and the j data line switching circuits DLSWi, are formed by the second wiring layer in the second direction. The j main data lines MDL_Aj for auto are connected to j amplifier circuits SA_Aj for auto. Here, xe2x80x9cautoxe2x80x9d is used to mean verifying cell data automatically in the memory system.
In the above-described arrangement, selection of the cell is performed as follows.
One row line WL is selected by the main row selection decoder RM0 and the sub row line selection decoder RS0 according to an address signal. And block selection and column selection are performed by the block decoder BD0 according to the address signal, and the column line BL is connected to the sub data line SDLj.
In case of reading data, by switching control of the data line switching circuits DLSW0 to DLSWk, the sub data lines SDLj are connected to the amplifier circuits SA_Rj for read through the main data lines MDL_Rj for read. The read of the cell data by the amplifier circuits SA_Rj for read is performed simultaneously correspondent to the number of output circuits (not shown), for example, byte data of eight lines or word data of sixteen lines.
In case of writing or erasing data, by switching control of the data line switching circuits DLSW0 to DLSWk, the sub data lines SDLj are connected to the amplifier circuits SA_Aj for auto through the main data lines MDL_Aj for auto. A check of a write or erase level of the cell is automatically performed by a control circuit (not shown). In this case, the erase of data is performed by a block circuit unit, the block decoder BDi controls such as electric potential control of the source line in case of erasing data.
According to the above-described arrangement, in case that a block in a bank (for example the bank BNK0) is being erased, the sub data lines SDLj in the bank BNK0 are connected to the main data lines MDL_Aj for auto by the data line switching circuit DLSW0 of the bank BNK0. In case that data of other bank (for example the bank BNKk) are wanted to read at the same time, it is possible to read the data of the bank BNKk in a manner that the sub data lines SDLj in the bank BNKk are connected to the main data lines MDL_Rj for read by the data line switching circuit DLSWk of the bank BNKk.
Recently, by demands for high speed of effective read cycle of the flash memory, high performance is required for a device operating in page mode and a device operating in burst mode. These devices have specifications that, for example, data are read together by eight words as one page and outputted serially by a word unit, so that many data lines (SDLj, MDL_Rj and MDL_Aj) are required.
FIG. 6 shows a pattern layout of a wiring layer in case that the flash memory shown in FIG. 5 is realized by using double layer metal wiring.
In the figure, row lines WLi which are output of sub row selection decoder RSi are made of poly crystalline silicon layer PoSi, column lines BLi are made of a metal M1 of a first layer. Main row selection lines Mi which are output of main row selection decoders RMi are made of a metal M2 of a second layer on cell arrays MAi. Sub data lines SDLj are made of the metal M2 of the second layer on column selection gates CGi or on a side of the column selection gates CGi. Main data lines MDL_Rj for read and main data lines MDL_Aj for auto are made of the metal M2 of the second layer on a power supply decoder VDDi or on a side of the power supply decoder VDDi.
However, in this layout of the wiring layer, as increasing each data line (SDLj, MDL_Rj and MDL_Aj) in the above-described device correspondent to dual work, a chip area of the semiconductor memory device is increases by the increased area for the device correspondent to dual work.
When the device operating in dual work is realized by using the double layer metal wiring, assuming that a pitch of the metal M2 of the second layer, for example, is 1 xcexcm, the chip area of the device will be discussed in case that two shield lines (CND electric potential) are added to a side of the data lines. That each cell array MAi includes a cell of 512K bits, each bank BNKi includes eight block circuit groups (a cell of 4M bits) and there are eight banks BNKi (a cell of 32M bits) in the device chip will be considered as an example.
In this case, each of data lines (SDLj, MDL_Rj and MDL_Aj) has (8+2) lines in a device reading by a byte unit, so that the occupied area of the data line DLA becomes about 10 xcexcm, though a ratio of the occupied area of the data line DLA to the chip area is small. In a device reading by a word unit, each of data lines (SDLj, MDL_Rj and MDL_Aj) has (16+2) lines, so that the occupied area of the data line DLA becomes about 18 xcexcm, though the ratio of the occupied area of the data line DLA to the chip area is also small.
However, for example, in the device operating in page mode of eight word which one word is one page (eight page device), since each of data lines (SDLj, MDL_Rj and MDL_Aj) has (128+2) lines, the occupied area of the data line DLA becomes about as much as 128 xcexcm, which causes the ratio of the occupied area of the data line DLA to the chip area not to be neglected. This results in an increase of the chip area and a rising cost of production.
As described above, there is a problem that the data lines remarkably increases and the chip area also increases by the increase of the data line area, in case that the device operating in page mode correspondent to dual work is realized to the conventional semiconductor memory device by using the double layer metal wiring.
According to an aspect of the present invention, there is provided a semiconductor memory circuit comprising a plurality of memory cell blocks arranged in a first direction, each of the memory cell blocks including a plurality of memory cells arranged in a matrix form, the plurality of memory cells being of MOS structure and being electrically data rewritable; a plurality of bit lines formed of a plurality of first wiring layers, a plurality of sub data lines formed of a plurality of second wiring layers, the plurality of sub data lines extending in the first direction on the plurality of memory cell blocks and being connected to the plurality of memory cell blocks; a first bank region including at least the plurality of memory cell blocks and the plurality of sub data lines; at least one of second bank region arranged in a second direction perpendicular to the first direction, the second bank region having the same structure as the first bank region; a plurality of data read lines formed of third wiring layers and arranged on the first and second bank regions, the plurality of data read lines configured so that data are read by way of the plurality of data lines from the plurality of memory cells of a bank region of the first and second bank regions selected in a first operation mode; a plurality of first amplifier circuits connected to the plurality of data read lines; a plurality of auto data lines extending in the second direction on a region out of the plurality of memory cell blocks of the first and second bank regions, the plurality of auto data lines configured so that data are read in a second operation mode by way of the plurality of sub data lines from the plurality of memory cells; a plurality of second amplifier circuits connected to the plurality of auto data read lines; a plurality of switch circuits provided in correspondence to the plurality of memory cell blocks of the first and second bank regions, the plurality of switch circuits configured to switch the plurality of sub data lines of the first and second bank regions and the plurality of data read lines between a connection state and a non-connection state in correspondence to the first and second operation modes, wherein data in the plurality of memory cells of the second bank region are readable from the plurality of first amplifier circuits, even when data in the plurality of memory cells of the first bank region is being read from the plurality of second amplifier circuits.